You cannot do a conditional branch without first setting the condition register somehow. This can be done with cmp or by adding s to most instructions. Check out the ARM assembly documentation for details. Quick example: Branch if r0 greater than 5: Compare r6 with r4 , put difference into r7, branch if r7 < 0:
As others have pointed out, LEA (load effective address) is often used as a “trick” to do certain computations, but that’s not its primary purpose. The x86 instruction set was designed to support high-level languages like Pascal and C, where arrays—especially arrays of ints or small structs—are common. Consider, for example, a struct representing (x, … Read more
AT&T syntax splits the movzx Intel instruction mnemonic into different mnemonics for different source sizes (movzb vs. movzw). In Intel syntax, it’s: i.e. load a byte from memory at eax+ecx+1 and zero-extend to full register. BTW, most GNU tools now have a switch or a config option to prefer Intel syntax. (Such as objdump -Mintel or gcc -S -masm=intel, although the latter affects … Read more
There’s a good guide to x87 FPU by Raymond Filiatreault. Chapter 1 explains how the FPU register stack works. Yes, fld st(0) pushes a copy of the top of the stack. The Intel insn ref manual explicitly mentions this special-case use of fld st(n) I believe you’re right that fstp does pop after the fild. The first fild / fstp pair converts a global int (at L1000F140) to a … Read more
CMP subtracts the operands and sets the flags. Namely, it sets the zero flag if the difference is zero (operands are equal). TEST sets the zero flag, ZF, when the result of the AND operation is zero. If two operands are equal, their bitwise AND is zero when both are zero. TEST also sets the sign flag, SF, when the most … Read more
There is no real reason why you should. Remember that EAX is only a 32-bit register, while all the FPU registers are 80 bits in width, because the FPU does calculations on 80-bit floats by default. Therefore, moving data from the FPU register to a general purpose register will cause data loss. If you really want to … Read more
A corresponding C function would be something like Specifically, the movzbl instruction fetches the byte stored at the sum of the two parameters, zero pads it, and stores it into eax. The movsbl instruction takes the lowest byte of eax, sign extends it, and stores the result back in eax.
As others have pointed out, LEA (load effective address) is often used as a “trick” to do certain computations, but that’s not its primary purpose. The x86 instruction set was designed to support high-level languages like Pascal and C, where arrays—especially arrays of ints or small structs—are common. Consider, for example, a struct representing (x, … Read more
AT&T syntax splits the movzx Intel instruction mnemonic into different mnemonics for different source sizes (movzb vs. movzw). In Intel syntax, it’s: i.e. load a byte from memory at eax+ecx+1 and zero-extend to full register. BTW, most GNU tools now have a switch or a config option to prefer Intel syntax. (Such as objdump -Mintel or gcc -S -masm=intel, although the latter affects … Read more
lw (load word) loads a word from memory to a register. $2 is the destination register and $4 the address register. And the source of information is the memory. 4 is an offset that is added (not multiplied) to the address register. This kind of memory access is called based addressing and is it quite … Read more