Verilog Testbench Clock

 initial begin 
    forever begin
    clk = 0;
    #10 clk = ~clk;
 end end

Try moving clk=0 above the forever loop. Instead of toggling the clock every #10 you’re resetting the clock to 0 every #10 units, and then toggling it instantly. I think that still might work in some cases, but it’s probably not what you intended to do.

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