What is the difference using NOP and stalls in MIPS

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I think you’ve got your terminology confused.

A stall is injected into the pipeline by the processor to resolve data hazards (situations where the data required to process an instruction is not yet available. A NOP is just an instruction with no side-effect.

Stalls

Recall the 5 pipeline stage classic RISC pipeline:

  1. IF – Instruction Fetch (Fetch the next instruction from memory)
  2. ID – Instruction Decode (Figure out which instruction this is and what the operands are)
  3. EX – Execute (Perform the action)
  4. MEM – Memory Access (Store or read from memory)
  5. WB – Write back (Write a result back to a register)

Consider the code snippet:

add $t0, $t1, $t1
sub $t2, $t0, $t0

From here it is obvious that the second instruction relies on the result of the first. This is a data hazard: Read After Write (RAW); a true dependency.

The sub requires the value of the add during its EX phase, but the add will only be in its MEM phase – the value will not be available until the WB phase:

+------------------------------+----+----+----+-----+----+---+---+---+---+
|                              |         CPU Cycles                      |
+------------------------------+----+----+----+-----+----+---+---+---+---+
|         Instruction          | 1  | 2  | 3  | 4   | 5  | 6 | 7 | 8 | 9 |
+------------------------------------------------------------------------+
|       0 | add $t0, $t1, $t1  | IF | ID | EX | MEM | WB |   |   |   |   |
|       1 | sub $t2, $t0, $t0  |    | IF | ID | EX  |    |   |   |   |   |
+---------+--------------------+----+----+----+-----+----+---+---+---+---+

One solution to this problem is for the processor to insert stalls or bubble the pipeline until the data is available.

+------------------------------+----+----+----+-----+----+----+-----+---+----+
|                              |         CPU Cycles                          |
+------------------------------+----+----+----+-----+----+----+-----+----+---+
|         Instruction          | 1  | 2  | 3  | 4   | 5  | 6  | 7   | 8  | 9 |
+----------------------------------------------------------------------------+
|        0 | add $t0, $t1, $t1 | IF | ID | EX | MEM | WB |    |     |    |   |
|        1 | sub $t2, $t0, $t0 |    | IF | ID | S   | S  | EX | MEM | WB |   |
+----------+-------------------+----+----+----+-----+----+---+---+---+-------+

NOPs

A NOP is an instruction that does nothing (has no side-effect). MIPS assembler often support a nop instruction but in MIPS this is equivalent to sll $zero $zero 0.

This instruction will take up all 5 stages of pipeline. It is most commonly used to fill the branch delay slot of jumps or branches when there is nothing else useful that can be done in that slot.

j label
nop # nothing useful to put here

If you are using a MIPS simulator you may need to enable branch delay slot simulation to see this. (For example, in spim use the -delayed_branches argument)

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