What does “all” stand for in a makefile?

A build, as Makefile understands it, consists of a lot of targets. For example, to build a project you might need

1. Build file1.o out of file1.c
2. Build file2.o out of file2.c
3. Build file3.o out of file3.c
4. Build executable1 out of file1.o and file3.o
5. Build executable2 out of file2.o

If you implemented this workflow with makefile, you could make each of the targets separately. For example, if you wrote

make file1.o

it would only build that file, if necessary.

The name of all is not fixed. It’s just a conventional name; all target denotes that if you invoke it, make will build all what’s needed to make a complete build. This is usually a dummy target, which doesn’t create any files, but merely depends on the other files. For the example above, building all necessary is building executables, the other files being pulled in as dependencies. So in the makefile it looks like this:

all: executable1 executable2

all target is usually the first in the makefile, since if you just write make in command line, without specifying the target, it will build the first target. And you expect it to be all.

all is usually also a .PHONY target. Learn more here.