Passing additional variables from command line to make

You have several options to set up variables from outside your makefile:

• From environment – each environment variable is transformed into a makefile variable with the same name and value. You may also want to set -e option (aka --environments-override) on, and your environment variables will override assignments made into makefile (unless these assignments themselves use the override directive . However, it’s not recommended, and it’s much better and flexible to use ?= assignment (the conditional variable assignment operator, it only has an effect if the variable is not yet defined): FOO?=default_value_if_not_set_in_environment Note that certain variables are not inherited from environment:
  • MAKE is gotten from name of the script
  • SHELL is either set within a makefile, or defaults to /bin/sh (rationale: commands are specified within the makefile, and they’re shell-specific).
• From command line – make can take variable assignments as part of his command line, mingled with targets: make target FOO=bar But then all assignments to FOO variable within the makefile will be ignored unless you use the override directive in assignment. (The effect is the same as with -e option for environment variables).
• Exporting from the parent Make – if you call Make from a Makefile, you usually shouldn’t explicitly write variable assignments like this: # Don't do this! target: $(MAKE) -C target CC=$(CC) CFLAGS=$(CFLAGS) Instead, better solution might be to export these variables. Exporting a variable makes it into the environment of every shell invocation, and Make calls from these commands pick these environment variable as specified above. # Do like this CFLAGS=-g export CFLAGS target: $(MAKE) -C target You can also export all variables by using export without arguments.