A build, as Makefile understands it, consists of a lot of targets. For example, to build a project you might need Build file1.o out of file1.c Build file2.o out of file2.c Build file3.o out of file3.c Build executable1 out of file1.o and file3.o Build executable2 out of file2.o If you implemented this workflow with makefile, … Read more
If you don’t specify a target on the command-line, Make uses the first target defined in the makefile by default. In your case, that is makefile:. But that doesn’t do anything. So just remove makefile:.
Question SOLVED: i had makefile in my directory as Makefile.mak I typed in Cygwin make -f Makefile.mak
‘gmake’ refers specifically to GNU make. ‘make’ refers to the system’s default make implementation; on most Linux distros this is GNU make, but on other unixes, it could refer to some other implementation of make, such as BSD make, or the make implementations of various commercial unixes. The language accepted by GNU make is a … Read more
Makefile requires that all “commands” in a rule are indented by one tab. You have, for example, this rule: That is wrong, the command-line should be intended with an actual tab (not spaces) like
I think you are confused about how the compiler puts things together. When you use -c flag, i.e. no linking is done, the input is C++ code, and the output is object code. The .o files thus don’t mix with -c, and compiler warns you about that. Symbols from object file are not moved to other object files like that. All object … Read more
Ok my edit solved the problem: placing a dash – in front of include hides the error messages coming from the dependency generation. Note for later: don’t try to outsmart Make.
If you’ve exported the environment variable: you can simply refer to it by name in the makefile (make imports all the environment variables you have set): If you’ve not exported the environment variable, it is not accessible until you do export it, or unless you pass it explicitly on the command line: If you are using a C … Read more
Could you provide a whole makefile? But right now I can tell – you should check that “install” target already exists. So, check Makefile whether it contains a line. If not, there is no such target and so make has right. Probably you should use just “make” command to compile and then use it as … Read more
The errors that you’re getting are linker errors, telling you that while linking your program the linker can’t find a function named ‘CreateSet’ (etc.). It’s not immediately obvious why that should be the case, because it appears that you’re including “set.o” in the build command. To troubleshoot build problems, it’s often useful to figure out … Read more