always is the main type of process from Verilog, the other is an initial which is ran once at the start of a simulation. always_ff @(posedge clk) :Represents a flip-flop (ff), the process is triggered (executed) on every positive edge of the clock. This replaces always @(posedge clk). This is the only type where non-blocking (<=) assignments should be used, … Read more
Verilog thinks in bits, so reg [7:0] a[0:3] will give you a 4×8 bit array (=4×1 byte array). You get the first byte out of this with a[0]. The third bit of the 2nd byte is a[1][2]. For a 2D array of bytes, first check your simulator/compiler. Older versions (pre ’01, I believe) won’t support … Read more
In this case the loop blocks until the expression (vif.xn_valid == 1’b1) is true, then it blocks until there is a posedge on vif.clk. A wait statement blocks until the condition is true. If the condition is already true then execution carries on immediately. In this case: the loop blocks until the expression (vif.cyc_tic == … Read more
empty and full are declared as output, which means their implied type is wire. You can only drive wires with a continuous assign: If you want to assign these signals from an always block, you should explicitly declare them as logic (or reg if you’re using Verilog):