System Verilog- Wait statements

In this case

forever begin
    wait (vif.xn_valid == 1'b1);
    @(posedge vif.clk);
end

the loop blocks until the expression (vif.xn_valid == 1'b1) is true, then it blocks until there is a posedge on vif.clk.

A wait statement blocks until the condition is true. If the condition is already true then execution carries on immediately.

In this case:

forever begin
    wait(vif.cyc_tic == 1'b1) @(posedge vif.clk) #0 fact_log2_samp_t = vif.fact_log2_samp;
end

the loop blocks until the expression (vif.cyc_tic == 1'b1) is true, then it blocks until there is a posedge on vif.clk. It is the same as:

forever begin
    wait(vif.cyc_tic == 1'b1);
    @(posedge vif.clk);
    #0 fact_log2_samp_t = vif.fact_log2_samp;
end