In NASM / Intel syntax, mov r64, 0x… picks a MOV encoding based on the constant. There are four to choose from with immediate operands: 5 byte mov r32, imm32. (zero-extended to fill the 64-bit register like always). AT&T: mov/movl 6+ byte mov r/m32, imm32. only useful for memory destinations. AT&T: mov/movl 7+ byte mov r/m64, sign-extended-imm32. Can store 8 bytes to memory, or set … Read more
A x64 native (AMD64 or Intel 64) processor is only mandated to support SSE and SSE2. SSE3 is supported by Intel Pentium 4 processors (“Prescott”), AMD Athlon 64 (“revision E”), AMD Phenom, and later processors. This means most, but not quite all, x64 capable CPUs should support SSE3. Supplemental SSE3 (SSSE3) is supported by Intel … Read more
I was reading the following definition for syscall: I saw it explained that the line cmpq $-4095 %rax determines whether %rax contains a value between -1 and -4095. How does it do that? What exactly does the cmpq instruction do?
General purpose means all of these registers might be used with any instructions doing computation with general purpose registers while, for example, you cannot do whatever you want with the instruction pointer (RIP) or the flags register (RFLAGS). Some of these registers were envisioned to be used for specific use, and commonly are. The most … Read more
It’s movsxd: https://www.felixcloutier.com/x86/MOVSX:MOVSXD.html. You could figure this out yourself by assembling it with an AT&T assembler and disassembling with an Intel-syntax disassembler. (e.g. objdumpd -d -Mintel foo.o) And yes, it does 32->64-bit 2’s complement sign extension, extending by copying the sign-bit of the source to all the new upper bits. (i.e. dst[63:32] = src[31], and dst[31:0] = src[31:0].) Fun fact: it’s … Read more
movq (assuming you’re talking about x86) is a move of a quadword (64-bit value). This particular instruction: looks very much like code that will walk up through stack frames. This particular instruction grabs the quadword pointed to by the current stack pointer, and loads it into the stack pointer, overwriting it. By way of example, this … Read more
RIP addressing is always relative to RIP (64bit Instruction Pointer) register. So it can be use for global variables only. The 0 offset is equal to address of the following instruction after the RIP-addressed instruction. For example: You wouldn’t normally mix data right in with your code, except as an immediate, but this shows what … Read more
It’s just call. Use Intel-syntax disassembly if you want to be able to look up instructions in the Intel/AMD manuals. The q operand-size suffix does technically apply (it pushes a 64-bit return address and treats RIP as a 64-bit register), but there’s no way to override it with instruction prefixes. i.e. calll and callw aren’t encodeable in 64-bit mode, so it’s just … Read more
According to my understanding cmpl compares unsigned. It does both, in a way. The difference in signed vs. unsigned is here the usage of the jump instructions. For >, there is ja for unsigned and jg for signed (jump if above and jump if greater). For <, there is jb for unsigned and jl for signed (jump if below and jump if less). To be exact, here … Read more
As others have pointed out, LEA (load effective address) is often used as a “trick” to do certain computations, but that’s not its primary purpose. The x86 instruction set was designed to support high-level languages like Pascal and C, where arrays—especially arrays of ints or small structs—are common. Consider, for example, a struct representing (x, … Read more